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fn9052 rev 2.00 page 1 of 18 nov 15, 2004 fn9052 rev 2.00 nov 15, 2004 isl6530 dual 5v synchronous buck pulse-width modulator (pwm) controller for ddram memory vddq and vtt termination datasheet the isl6530 provides complete control and protection for dual dc-dc converters optimiz ed for high-performance ddram memory applications. it is designed to drive low cost n-channel mosfets in synchronous-rectified buck topology to efficiently generate 2.5v v ddq for powering ddram memory, v ref for ddram differential signalling, and v tt for signal termination. the isl6530 integrates all of the control, output adjustment, monitoring and protection functions into a single package. the v ddq output of the converter is maintained at 2.5v through an integrated precisio n voltage reference. the v ref output is precisely regulated to 1/2 the memory power supply, with a maximum tolerance of ? 1% over temperature and line voltage variations. v tt accurately tracks v ref . during v2_sd sleep mode, the v tt output is maintained by a low power window regulator. the isl6530 provides simple, single feedback loop, voltage- mode control with fast transient response. it includes two phase-locked 300khz triangle-wave oscillators which are displaced 90 o to minimize interference between the two pwm regulators. the regulators feature error amplifiers with a 15mhz gain-bandwidth product and 6v/ ? s slew rate which enables high converter bandwidth for fast transient performance. the resulting pwm duty ratio ranges from 0% to 100%. the isl6530 protects against over-current conditions by inhibiting pwm operation. the isl6530 monitors the current in the v ddq regulator by using the r ds(on) of the upper mosfet which eliminates the need for a current sensing resistor. ordering information features ? provides v ddq , v ref , and v tt voltages for one- and two-channel ddram memory systems ? excellent voltage regulation -v ddq = 2.5v ? 2% over full operating range -v ref = (v ddq ? 2) ? 1% over full operating range -v tt = v ref ?? 30mv ? supports ?s3? sleep mode -v tt is held at v ddq ? 2 via low power window regulator to minimize wake-up time ? fast transient response - full 0% to 100% duty ratio ? operates from +5v input ? overcurrent fault monitor on vdd - does not require extra current sensing element - uses mosfet?s r ds(on) ? drives inexpensive n-channel mosfets ? small converter size - 300khz fixed frequency oscillator ? 24 lead, soic or 32 lead, 5mm ? 5mm qfn ? pb-free available (rohs compliant) applications ?v ddq , v tt , and vref regulation for ddram memory systems - main memory in amd? athlon? and k8?, pentium? iii, pentium iv, transmeta , powerpc?, alphapc?, and ultrasparc? based computer systems - video memory in graphics systems ? high-power tracking dc-dc regulators part number temp range( o c) package pkg. dwg. # isl6530cb* 0 to 70 24 lead soic m24.3 ISL6530CBZ* (see note) 0 to 70 24 lead soic (pb-free) m24.3 isl6530cr* 0 to 70 32 lead 5x5 qfn l32.5x5 isl6530crz* (see note) 0 to 70 32 lead 5x5 qfn (pb-free) l32.5x5 isl6530eval1, 2 evaluation board * add -t suffix for tape and reel option. note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termina tion finish, which are rohs compliant and compatible with both snpb and pb-free solder ing operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020c . n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
isl6530 fn9052 rev 2.00 page 2 of 18 nov 15, 2004 pinouts 24 lead (soic) top view 32 lead (qfn) top view 15 16 17 10 9 8 vref_in phase2 sense2 fb2 vcc gnda 18 19 20 21 22 23 24 7 6 5 4 3 2 1 boot1 phase1 fb1 sense1 vref pgnd1 pvcc1 ocset/sd v2_sd pgood comp2 lgate1 comp1 ugate1 13 14 12 11 ugate2 lgate2 pgnd2 boot2 boot1 boot1 ugate1 ugate1 pgnd1 pgnd1 lgate1 pvcc1 phase2 boot2 boot2 ugate2 pgnd2 pgnd2 lgate2 vcc phase 1 vref fb1 comp1 sense1 vref_in gnda gnda pvcc1 ocset/sd v2_sd pgood comp2 sense2 fb2 vcc 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910111213141516
isl6530 fn9052 rev 2.00 page 3 of 18 nov 15, 2004 block diagram oscillator soft- start inhibit pwm comparator error amp v cc pwm pgnd1 vref fb1 comp1 over- current gate control logic boot1 ugate1 phase1 40 ? a + - + - + - lgate1 ocset/sd pgood + - power-on reset (por) 90 o phase inhibit pwm comparator error amp pwm gnd gate control logic boot2 ugate2 phase2 + - + - lgate2 0.8v reference fb2 comp2 v2_sd window regulator pvcc1 vref_in sense1 shift pgnd2 vcc sense2 + - + - + - + - 0.85 x 1.15 x 0.85 x 1.15 x
isl6530 fn9052 rev 2.00 page 4 of 18 nov 15, 2004 typical application boot1 r fb2 +5v +5v reset v ref (.5xv ddq ) ugate1 phase1 pvcc1 lgate1 boot2 ugate2 phase2 lgate2 pgnd2 pgnd1 comp2 fb2 sense2 sense1 fb1 comp1 ocset/sd pgood vcc gnda v2_sd vref_in vref sleep r fb1 c out2 l out2 c out1 l out1 q 1 q 2 q 3 q 4 d boot1 d boot2 c boot2 c boot1 r ocset pgood isl6530 v ddq v tt figure 1. typical application for isl6530
isl6530 fn9052 rev 2.00 page 5 of 18 nov 15, 2004 absolute maximum rati ngs thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v boot voltage, v bootn - v phasen . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.3v to v cc +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v ? 10% ambient temperature range. . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c junction temperature range . . . . . . . . . . . . . . . . . . . 0 o c to 125 o c thermal resistance ? ja ( o c/w) ? jc ( o c/w) soic package (note 1) . . . . . . . . . . . . 65 n/a qfn package (note 2). . . . . . . . . . . . . 33 4 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) for recommended soldering conditions see tech brief tb389. caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ? ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. ? jc, the ?case temp? is measured at the center of the expos ed metal pad on the package underside. see tech brief tb379. electrical specifications recommended operating conditions with vcc = 5v, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current nominal supply i cc ocset/sd = v cc ; ugate1, ugate2, lgate1, and lgate2 open -5-ma shutdown supply ocset/sd = 0v - 3 - ma power-on reset rising v cc threshold v ocset/sd = 4.5v 4.25 - 4.5 v falling v cc threshold v ocset/sd = 4.5v 3.75 - 4.0 v oscillator free running frequency v cc = 5 275 300 325 khz references reference voltage (v2 error amp reference) v vref sense1 = 2.5v 49.5 50 50.5 %sense1 v1 error amp reference voltage tolerance --2 ? v1 error amp reference v ref v cc = 5 - 0.8 - v error amplifiers dc gain -82- db gain-bandwidth product gbw - 15 - mhz slew rate sr comp = 10pf - 6 - v/ ? s window regulator load current -10- ma output voltage error v2_sd = vcc; 10ma load on v2 - 7 % gate drivers upper gate source (ugate1 and 2) i ugate v cc = 5v, v ugate = 2.5v - -1 - a upper gate sink (ugate1 and 2) i ugate v ugate-phase = 2.5v - 1 - a lower gate source (lgate1 and 2) i lgate v cc = 5v, v lgate = 2.5v - -1 - a lower gate sink (lgate1 and 2) i lgate v lgate = 2.5v - 2 - a protection ocset/sd current source i ocset v ocset = 4.5vdc 34 40 46 ? a ocset/sd disable voltage v reset -0.8- v
isl6530 fn9052 rev 2.00 page 6 of 18 nov 15, 2004 functional pin description 24 lead (soic) top view 32 lead (qfn) top view boot1 and boot2 these pins provide bias voltage to the upper mosfet drivers. a single capacitor bootstrap circuit may be used to create a boot voltage suitable to drive a standard n- channel mosfet. ugate1 and ugate2 connect ugate1 and ugate2 to the corresponding upper mosfet gate. these pins prov ide the gate drive for the upper mosfets. ugate2 is also monitored by the adaptive shoot through protection to determine when the upper fet of the v tt regulator has turned off. lgate1 and lgate2 connect lgate1 and lgate2 to the corresponding lower mosfet gate. these pins prov ide the gate drive for the lower mosfets. these pins are monitored by the adaptive shoot through protection to determine when the lower fet has turned off. pgnd1 and pgnd2 these are the power ground connections for the gate drivers of the pwm controllers. tie these pins to the ground plane through the lowest impedence connection available. ocset/sd a resistor (r ocset ) connected from this pin to the drain of the upper mosfet of the v ddq regulator sets the overcurrent trip point. r ocset , an internal 40 ? a current source (i ocs ), and the upper mosfet on-resistance (r ds(on) ) set the v ddq converter over-current (oc) trip point according to the following equation: an overcurrent trip cycles the soft-start function. pulling the ocset/sd pin to ground resets the isl6530 and all external mosfets are turned off allowing the two output voltage power rails to float. pgood a high level on this open-drain output indicates that both the v ddq and v tt regulators are within normal operating voltage ranges. gnda signal ground for the ic. tie this pin to the ground plane through the lowest impedence connection available. vcc the 5v bias supply for the chip is connected to this pin. this pin is also the positive supply for the lower gate driver, lgate2. connect a well decoupled 5v supply to this pin. v2_sd a high level on the v2_sd input places the v2 controller into ?sleep? mode. in sleep mode, both ugate2 and lgate2 are driven low, effectively floating the v tt supply. 15 16 17 10 9 8 vref_in phase2 sense2 fb2 vcc gnda 18 19 20 21 22 23 24 7 6 5 4 3 2 1 boot1 phase1 fb1 sense1 vref pgnd1 pvcc1 ocset/sd v2_sd pgood comp2 lgate1 comp1 ugate1 13 14 12 11 ugate2 lgate2 pgnd2 boot2 boot1 boot1 ugate1 ugate1 pgnd1 pgnd1 lgate1 pvcc1 phase2 boot2 boot2 ugate2 pgnd2 pgnd2 lgate2 vcc phase 1 vref fb1 comp1 sense1 vref_in gnda gnda pvcc1 ocset/sd v2_sd pgood comp2 sense2 fb2 vcc 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910111213141516 i peak i ocs r ocset ? r ds on ?? ------------------------------------------- - =
isl6530 fn9052 rev 2.00 page 7 of 18 nov 15, 2004 while the v tt supply ?floats?, it is held to about 50% of v ddq via a low current window regulator which drives v tt via the sense2 pin. the window regulator can overcome up to at least ? 10ma of leakage on v tt . while v2_sd is high, pgood is low. phase1 and phase2 connect phase1 and phase2 to the corresponding upper mosfet source. this pin is used as part of the upper mosfet bootstrapped drives. phase1 is used to monitor the voltage drop across the upper mosfet of the v ddq regulator for over-current pr otection. the phase1 pin is monitored by the adaptive shoo t through protection circuitry to determine when the upper fet of the v ddq supply has turned off. fb1, comp1, fb2, and comp2 comp1, comp2, fb1, and fb2 are the available external pins of the error amplifiers. the fb1 and fb2 pins are the inverting inputs of each error amplifier and the comp1 and comp2 pins are the associated outputs. an appropriate ac network across these pins is used to compensate the voltage-controlled feedback loop of each converter. vref and vref_in vref produces a voltage equal to one half of the voltage on sense1. this low current output is connected to the vref input of the ddram devices being powered. this same voltage is used as the reference input of the v tt error amplifier. thus v tt is controlled to 50% of v ddq . vref_in is used as an option to overdrive the internal resistor divider network that sets the voltage for both vref_out and the reference voltage for the v tt supply. a 100pf capacitor between vref_in and ground is recommended for proper operation. pvcc1 this is the positive supply for the lower gate driver, lgate1. pvcc1 is connected to a well decoupled 5v. sense1 and sense2 both sense1 and sense2 are connected directly to the regulated outputs of the v ddq and v tt supplies, respectively. sense1 is used as an input to create the voltage at vref_out and the reference voltage for the v tt supply. sense2 is used as the regulation point for the window regulator that is enabled in v2_sd mode. functional description overview the isl6530 contains control and drive circuitry for two synchronous buck pwm voltage r egulators. both regulators utilize 5v bootstrapped output topology to allow use of low cost n-channel mosfets. the regulators are driven by 300khz clocks. the clocks are phase locked and displaced 90 o to minimize noise coupling between the controllers. the first regulator includes a precision 0.8v reference and is intended to provide the proper v ddq to a ddram memory system. the v ddq controller implem ents overcurrent protection utilizing the r ds(on) of the upper mosfet. following a fault condition, the v ddq regulator is softstarted via a digital softstart circuit. included in the isl6530 is a precision v ref reference output. v ref is a buffered representation of .5xv ddq . v ref is derived via a precision internal resistor divider connected to the sense1 terminal. the second pwm regulator is designed to provide v tt termination for the ddram signal lines. the reference to the v tt regulator is v ref . thus the v tt regulator provides a termination voltage equal to .5xv ddq . the drain of the upper mosfet of the v tt supply is connected to the regulated v ddq voltage. the v tt controller is designed to enable both sinking and sourcing current on the v tt rail. two benefits result from the isl6530 dual controller topology. first, as vref is always .5xv ddq , the v tt supply will track the v ddq supply during softstart cycles. second, the overcurrent protection incorporated into the v ddq supply will simultaneously protect the v tt supply. initialization the isl6530 automatically initializes upon application of input power. special sequencing of the input supplies is not necessary. the power-on reset (por) function continually monitors the input bias supply voltage at the vcc pin. the por function initiates soft-start operation after the 5v bias supply voltage exceeds its por threshold. soft-start the por function initiates the di gital soft start sequence. the pwm error amplifier reference input for the vddq regulator is clamped to a level proportional to the soft-start voltage. as the soft-start voltage slews up, the pwm comparator generates phase pulses of increasing width that charge the output capacitor(s). this method provides a rapid and controlled output voltage rise. the soft start sequence typically takes about 7ms. with the v tt regulator reference held at it will automatically track the ramp of the v ddq softstart, thus enabling a soft-start for v tt . figure 2 shows the soft-start sequ ence for a typical application. at t0, the +5v vcc bias voltag e starts to ramp. once the voltage on vcc crosses the por threshold at time t1, both outputs begin their soft-start sequence. the triangle waveforms from the pwm oscillators are compared to the rising error amplifier output voltage. as the error amplifier voltage increases, the pulse-widths on the ugate pins increase to reach their steady-state duty cycle at time t2. 1 2 -- - v ddq ?
isl6530 fn9052 rev 2.00 page 8 of 18 nov 15, 2004 shoot-through protection a shoot-through condition occurs when both the upper mosfet and lower mosfet are turned on simultaneously, effectively shorting the input voltage to ground. to protect the regulators from a shoot-t hrough condition, the isl6530 incorporates specialized ci rcuitry which insures that complementary mosfets are not on simultaneously. the adaptive shoot-through protection utilized by the v ddq regulator looks at the lower gate drive pin, lgate1, and the phase node, phase1, to determi ne whether a mosfet is on or off. if phase1 is be low 0.8v, the upper gate is defined as being off. similarly, if lgate1 is below 0.8v, the lower mosfet is defined as being off. this method of shoot-through protection allows the v ddq regulator to source current only. due to the necessity of sinking current, the v tt regulator employs a modified protection scheme from that of the v ddq regulator. if the voltag e from ugate2 or from lgate2 to gnd is less than 0.8v, then the respective mosfet is defined as being off and the other mosfet is turned on. since the voltage of the lowe r mosfet gates and the upper mosfet gate of the v tt supply are being measured to determine the state of the mosfet, the designer is encouraged to consider the repercussions of introducing external components between the gate drivers and their respective mosfet gates before actually implementing such measures. doing so may interfere with the shoot- through protection. power down mode ddram systems include a sleep state in which the v ddq voltage to the memories is maintained, but signaling is suspended. during this mode the v tt termination voltage is no longer needed. the only load placed on the v tt bus is the leakage of the associated signal pins of the ddram and memory controller ics. when the v2_sd input of the isl6530 is driven high, the v tt regulator is placed into a ?sleep? state. in the sleep state the main v tt regulator is disabled, with both the upper and lower mosfets being turned off. the v tt bus is maintained at close to .5 xvdd via a low current window regulator which drives v tt via the sense2 pin. maintaining v tt at .5xv ddq consumes negligible power and enables rapid wake-up from sleep mode without the need of softstarting the v tt regulator. during this power down mode, pgood is held low. output voltage selection the output voltage of the v ddq regulator can be programmed to any level between v in (i.e. +5v) and the internal reference, 0.8v. an external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the invertin g input of the error amplifier, see figure 3. however, since the value of r1 affects the values of the rest of the co mpensation components, it is advisable to keep its value less than 5k ? . r4 can be calculated based on the following equation: if the output voltage desired is 0.8v, simply route vout1 back to the fb pin through r1, but do not populate r4. v tt reference overdrive the isl6530 allows the designer to bypass the internal 50% tracking of v ddq that is used as the reference for v tt . the isl6530 was designed to divide down the v ddq voltage by 50% through two internal matched resistances. these resistances are typically 200k ? . figure 2. soft-start interval 0v time vcc (5v) (1v/div ) t1 t2 t0 v ddq (2.5v) v tt (1.25v) r4 r1 0.8v ? v out1 0.8v C ------------------------------------- - = figure 3. output voltage selection of v ddq + r1 c out1 +5v v ddq r4 l out isl6530 c4 q1 fb1 ugate1 vcc boot1 comp1 d1 r2 c2 c1 r3 c3 phase1 lgate1 q2
isl6530 fn9052 rev 2.00 page 9 of 18 nov 15, 2004 one method that may be employed to bypass the internal v tt reference generation is to supply an external reference directly to the v ref_in pin. when doing this the sense1 pin must remain unconnected. caution must be exercised when using this method as the v tt regulator does not employ a soft-start of its own. a second method would be to overdrive the internal resistors. figure 4 shows how to implement this method. the external resistors used to overdrive the internal resistors should be less than 2k ? and have a tolerance of 1% or better. this method still supplies a buffer between the resistor network and any loading on the v ref pin. if there is no loading on the v ref pin, then no buffering is necessary and the reference voltage created by the resistor network can be tied directly to v ref . converter shutdown pulling and holding the ocset/sd pin below 0.8v will shutdown both regulators. during this state, pgood will be held low. upon release of the ocset/sd pin, the ic enters into a soft start cycle wh ich brings both outputs back into regulation. voltage monitoring the isl6530 offers a pgood signal that will communicate whether the regulation of both v ddq and v tt are within 15% of regulation, the v2_sd pin is held low and the bias voltage of the ic is above the por level. if all the criteria above are true, the pgood pin will be at a high impedence level. when one or more of the criteria listed above are false, the pgood pin will be held low. overcurrent protection the overcurrent function protects the converter from a shorted output by using the upper mosfet on-resistance, r ds(on) , of v ddq to monitor the current. this method enhances the converter?s efficiency and reduc es cost by eliminating a current sensing resistor. the over-current function cycles the soft-start function in a hiccup mode to provide fault protection. a resistor (r ocset ) programs the overcurrent trip le vel (see figure 1). an internal 40 ? a (typical) current sink develops a voltage across r ocset that is referenced to v in . when the voltage across the upper mosfet of v ddq (also referenced to v in ) exceeds the voltage across r ocset , the overcurrent function initiates a soft-start sequence. figure 5 illustrates the protection feature responding to an over current event on v ddq . at time t0, an over current condition is sensed across the upper mosfet of the v ddq regulator. as a result, both regulators are quickly shutdown and the internal soft-start function begins producing soft- start ramps. the delay interval seen by the output is equivalent to three soft-start cycles. the fourth internal soft- start cycle initiates a normal soft -start ramp of the output, at time t1. both outputs are brought back into regulation by time t2, as long as the overcurrent event has cleared. had the cause of the overcurrent still been present after the delay interval, the overcurrent condition would be sensed and both regulators would be shut down again for another delay interval of three soft-s tart cycles. the resulting hiccup mode style of protection wo uld continue to repeat indefinitely. the overcurrent function will trip at a peak inductor current (i peak) determined by: where i ocset is the internal ocset current source (40 ? a typical). the oc trip point varies mainly due to the mosfet figure 4. v tt reference overdrive vref + - vref_in sense1 to error amplifier isl6530 v ddq r a r b figure 5. overcurrent protection response 0v time v ddq (2.5v) t1 t0 t2 v tt (1.25v) internal soft-start function delay interval i peak i ocset x r ocset r ds on ?? ---------------------------------------------------- - =
isl6530 fn9052 rev 2.00 page 10 of 18 nov 15, 2004 r ds(on) variations. to avoid over-current tripping in the normal operating load range, find the r ocset resistor from the equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for , where ?? i is the output inductor ripple current. for an equation for the ripple current see the section under component guidelines titled output inductor selection . a small ceramic capacitor should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input voltage. current sinking the isl6530 v tt regulator incorporates a mosfet shoot- through protection method which a llows the converter to sink current as well as source current. care should be exercised when designing a converter with the isl6530 when it is known that the converter may sink current. when the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. this means that the converter is boosting current into the input rail of the regulator. if there is nowhere for this current to go, such as to other distributed loads on the rail or through a voltage limiting protection devic e, the capacitance on this rail will absorb the current. this situation will allow the voltage level of the input rail to increa se. if the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of any components attach ed to the input rail, then those components may experience an irreversible failure or experience stress that may sh orten their lifespan. ensuring that there is a path for the current to flow other than the capacitance on the rail will prevent this failure mode. to insure that the current does not boost up the input rail voltage of the v tt regulator, it is recommended that the input rail of the v tt regulator be the output of the v ddq regulator. the current being sunk by the v tt regulator will be fed into the v ddq rail and then drawn into the ddr sdram memory module and back into the v tt regulator. figure 6 shows the recommend ed configuration and the resulting current loop. application guidelines layout considerations layout is very important in high frequency switching converter design. with power dev ices switching efficiently at 300khz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes the voltage spikes in the converters. as an example, consider the turn-off transition of the pwm mosfet. prior to turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is picked up by the lower mosfet. any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critic al components, and short, wide traces minimi zes the magnitude of voltage spikes. there are two sets of critical components in a dc-dc converter using the isl6530. the switching components are the most critical because t hey switch large amounts of energy, and therefore tend to generate large amounts of noise. next are the small si gnal components which connect to sensitive nodes or supply critical bypass current and signal coupling. a multi-layer printed circuit board is recommended. figure 7 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power i peak i out max ?? ? i ?? 2 ---------- + ? figure 6. v tt current sinking loop ddr sdram +5v r t + - v ref ugate1 lgate1 phase1 ugate2 lgate2 phase2 isl6530 v ddq v tt
isl6530 fn9052 rev 2.00 page 11 of 18 nov 15, 2004 nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the gate pins to the mosfet gates should be kept short and wide enough to easily handle the 1a of drive current. the switching components should be placed close to the isl6530 first. minimize the length of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper mosfet and lower diode and the load. the critical small signal components include any bypass capacitors, feedback components, and compensation components. position the bypass capacitor, c bp , close to the vcc pin with a via directly to the ground plane. place the pwm converter compensation co mponents close to the fb and comp pins. the feedback resistors for both regulators should also be located as close as possible to the relevant fb pin with vias tied straight to the ground plane as required. feedback compensation figure 8 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (err or amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse- width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage ? v osc modulator break frequency equations the compensation network consis ts of the error amplifier (internal to the isl6530) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees. the equations below relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 7. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place first zero below filter?s double pole (~75% f lc ). 3. place second zero at filter?s double pole. 4. place first pole at the esr zero. 5. place second pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin - repeat if necessary. v ddq island on power plane layer island on circuit plane layer l out1 c out1 c in +5v v in key comp1 isl6530 ugate1 r4 r 2a c bp fb1 gnd vcc figure 7. printed circuit board power planes and islands r 1a boot1 c 2a via connection to ground plane load q1 c boot1 phase1 d1 r 3a c 3a c 1a q2 lgate1 phase1 v tt l out2 c out2 ugate2 load q3 c boot2 phase2 q4 lgate2 phase2 +5v v in boot2 d2 v ddq sense1 pgnd1 pgnd2 comp1 r 2b fb1 r 1b c 2b r 3b c 3b c 1b sense2 f lc 1 2 ? x l o x c o ----------------------------------------- - = f esr 1 2 ? x esr x c o ------------------------------------------- =
isl6530 fn9052 rev 2.00 page 12 of 18 nov 15, 2004 . compensation break frequency equations figure 9 shows an asymptotic plot of the dc-dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 9. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the graph of figure 9 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable contro l loop has a gain crossing with -20db/decade slope and a phase margin greater than 45 degrees. include worst case component variations when determining phase margin. component selection guidelines output capacitor selection an output capacitor is required to filter the ou tput and supply the load transient current. t he filtering requirements are a function of the switching fr equency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern digital ics can produce high transient load slew rates. high-frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor val ues are generally determined by the esr (effective series resistance) and voltage rating requirements rather than ac tual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-es r capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determi ne the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr avai lable in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. figure 8. voltage-mode buck converter compensation design v out reference l o c o esr v in dv osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 2 c 3 c 1 c 2 comp v out fb z fb isl6530 z in comparator driver detailed compensation components phase v e/a + - + - z in osc f z2 1 2 ? x r 1 r 3 + ?? x c 3 ------------------------------------------------------ - = f p1 1 2 ? x r 2 x c 1 x c 2 c 1 c 2 + --------------------- - ?? ?? ?? -------------------------------------------------------- - = f p2 1 2 ? x r 3 x c 3 ------------------------------------ = f z1 1 2 ? r 2 ? c 2 ? ---------------------------------- = figure 9. asymptotic bode plot of converter gain 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain modulator gain loop gain 20 v in v osc --------------- - ?? ?? ?? log 20 r2 r1 ------- - ?? ?? log
isl6530 fn9052 rev 2.00 page 13 of 18 nov 15, 2004 output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time re quired to change the inductor current. given a sufficiently fast control loop design, the isl6530 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor cu rrent from an initial current value to the transient current le vel. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosf ets. use small ceramic capacitors for high frequency de coupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors physic ally close to the mosfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rm s current rating requirement for the input capacitor of a bu ck regulator is approximately 1/2 the dc load current. the maximum rms current requir ed by the regulator may be closely approximated through the following equation: for a through-hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but ca ution must be exercised with regard to the capacitor surge currentrating. these capacitors must be capable of handling t he surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. mosfet selection/considerations the isl6530 requires two n-channel power mosfets for each pwm regulator. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor. the switching losses seen when sourcing current will be different from the switching losses seen when sinking current. the v ddq regulator will only source current while the v tt regulator can sink and source. when sourcing current, the upper mosfet realizes most of the switching lo sses. the lower switch realizes most of the switching losses when the converter is sinking current (see the equations below). these equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower mosfet?s body diode. the gate-charge losses are dissipated by the isl6530 and don't heat the mosfets. however, large gate-charge increases th e switching interval, t sw which increases the mosfet switching losses. ? i = v in - v out f s x l v out v in ? v out = ? i x esr x t rise = l x i tran v in - v out t fall = l x i tran v out i rms max v out v in ------------- - i out max 2 1 12 ------ v in v out C lf s ? ---------------------------- - v out v in ------------- - ? ?? ?? 2 ? + ?? ?? ? = ?? ? 1d C ?? ? 1 2 -- - io ? v in ? t sw f s ? ? + = p upper io 2 r ds on ?? ? d ? 1 2 -- - io ? v in ? t sw f s ? ? + = p upper = io 2 x r ds(on) x d
isl6530 fn9052 rev 2.00 page 14 of 18 nov 15, 2004 ensure that both mosfets are within their maximum junction temperature at high ambient te mperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. given the reduced available gate bias voltage (5v), logic- level or sub-logic-level transistors should be used for both n- mosfets. caution should be exercised when using devices with very low gate thresholds (v th ). the shoot-through protection circuitry may be circumvented by these mosfets. very high dv/dt transitions on the phase node may cause the miller capacitance to couple the lower gate with the phase node and cause an undesireable turn on of the lower mosfet while the upper mosfet is on. bootstrap component selection external bootstrap components, a diode and capacitor, are required to provide sufficient gate enhancement to the upper mosfet. the internal mosfet gate driver is supplied by the external bootstrap circuitry as shown in figure 10. the boot capacitor, c boot , develops a floating supply voltage referenced to the phase pin. this supply is refreshed each cycle, when d boot conducts, to a voltage of vcc less the boot diode drop, v d , plus the voltage rise across q lower . just after the pwm switching cycle begins and the charge transfer from the bootstrap capa citor to the gate capacitance is complete, the voltage on the bootstrap capacitor is at its lowest point during the switching cycle. the charge lost on the bootstrap capacitor will be equal to the charge transferred to the equivalent gate-source capacitance of the upper mosfet as shown: where q gate is the maximum total gate charge of the upper mosfet, c boot is the bootstrap capacitance, v boot1 is the bootstrap voltage immediately before turn-on, and v boot2 is the bootstrap voltage immediately after turn-on. the bootstrap capacitor begins its refresh cycle when the gate drive begins to turn-off the upper mosfet. a refresh cycle ends when the upper mosfet is turned on again, which varies depending on the switching frequency and duty cycle. the minimum bootstrap capaci tance can be ca lculated by rearranging the previous e quation and solving for c boot . typical gate charge values for mosfets considered in these types of applications range from 20 to 100nc. since the voltage drop across q lower is negligible, v boot1 is simply vcc - v d . a schottky diode is recommended to minimize the voltage drop across the bootstrap capacitor during the on-time of the upper mosfet. initial calculations with v boot2 no less than 4v will quickly help narrow the bootstrap capacitor range. for example, consider an upper mosfet is chosen with a maximum gate charge, q g , of 100nc. limiting the voltage drop across the bootstrap capacitor to 1v results in a value of no less than 0.1 ? f. the tolerance of the ceramic capacitor should also be considered wh en selecting the final bootstrap capacitance value. a fast recovery diode is recommended when selecting a bootstrap diode to reduce the impact of reverse recovery charge loss. otherwise, the recovery charge, q rr , would have to be added to the gate charge of the mosfet and taken into consideration when calculating the minimum bootstrap capacitance. isl6530 gnd lgaten ugaten phasen bootn v in note: note: v g-s a v cc c boot d boot q upper q lower + - figure 10. upper gate drive bootstrap v g-s a v cc -v d + v d - vcc q gate c boot v boot1 v boot2 C ?? ? = C boot2 ---------------------------------------------------- - ?
isl6530 fn9052 rev 2.00 page 15 of 18 nov 15, 2004 isl6530 dc-dc converter application circuit figure 11 shows an application circuit for a ddr sdram power supply, including v ddq (+2.5v) and v tt (+1.25v). detailed information on the circui t, including a complete bill- of-materials and circuit board description, can be found in application note an9993. component selection notes: c4,5,7,8,9,10,18,19 - each 150mf, panasonic eef-ue0j151r d1,2 - each 30ma schottky diode, ma732 l1,2 - each 1mh inductor, panasonic p/n etq-p6f1rosfa q1,2 - each fairchild mosfet; itf86130dk8 q3 - fairchild mosfet; itf86110dk8 figure 11. ddr sdram voltage regulator boot1 r 21 +5v ugate1 phase1 pvcc1 lgate1 boot2 ugate2 phase2 lgate2 pgnd2 pgnd1 comp2 fb2 sense2 sense1 fb1 comp1 ocset/sd pgood vcc gnda v2_sd vref_in vref r 19 c 18,19 l 2 c 7,8,9,10 l 1 q 1 q 2 q 3 d 1 d 2 c 16 c 6 r 1 isl6530 v ddq v tt c 1 c 2 c 4,5 c 15 c 17 r 23 r 22 c 22 c 24 c 23 c 26 r 26 c 25 r 25 c 27 @5a @10a r 20 c 30 1000pf 3.48k ? 0.1 ? f c 3 1.0 ? f 150 ? f(x2) 0.1 ? f 1 ? h 150 ? f(x4) 0.1 ? f 1.0 ? f 0.1 ? f 1 ? h 150 ? f(x2) 68pf 3.01k ? 158 ? 8.87k ? 2700pf 10000pf 1.43k ? 15000pf 100pf 5600pf 6.34k ? 3.01k ? 100 ? 100pf
fn9052 rev 2.00 page 16 of 18 nov 15, 2004 isl6530 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2002-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners.
isl6530 fn9052 rev 2.00 page 17 of 18 nov 15, 2004 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 ? 0 o 8 o 0 o 8 o - rev. 0 12/93
isl6530 fn9052 rev 2.00 page 18 of 18 nov 15, 2004 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l32.5x5 32 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-2 issue c symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n322 nd 8 3 ne 8 8 3 p- -0.609 ? --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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